VLSI Test and Testability (Syllabus)

 VLSI Test and Testability

Course Code: 6TMVD-203

COURSE OBJECTIVE:

The objective of this course is to provide students with a sound knowledge of VLSI systems covering the following:

  • Processor architectures, memory organization and performance analysis, and concepts and techniques for parallel processing and pipeline processing.
  • High-speed synchronization design and system noise consideration.

 

Syllabus:

UNIT – I Introduction to Testing Process: CMOS Testing, Reliability, Failures & Faults, Levels of Testing, Test economics, Elementary Testing Concepts, System and Field Testing, Burn in boards.

UNIT - II   Logic Simulation & Fault modelling: Delay Models, Event driven simulation, general fault emulation, fault detection and redundancy, fault equivalence and fault dominance. Stuck-at faults, bridging faults, transistor faults, delay faults etc. Fault detection using Boolean Difference, Path Sensitization. Fault Collapsing.

UNIT - III Test generation for combinational & sequential circuits: D-algorithm, PODEM, SPOOF. Automatic Test Pattern Generation. Primitive and Propagation Cubes. Fan-out Oriented Test Generation. Controllability and Observe ability. Testing of sequential circuits as iterative combinational circuits, state table verification, random testing.

UNIT - IV  Design for testability: Ad-hoc methods, Full scan & Partial scan design. Boundary scans. Testability analysis.

UNIT -V    Built-in self-test & IDDQ testing: RAM BIST, Logic BIST Random and weighted random pattern testability BIST Pattern generator and response analyzer Scan-based BIST architecture Test point insertion for improving random testability. IDDQ testing, IDDQ test patterns, IDDQ measurement Case studies, Design for IDDQ testability.

COURSE OUTCOME:

After the completion of this course, the students are able to:

  • ·         Acquire knowledge about fault modeling and collapsing.
  • ·         Learn about various combinational atpg.
  • ·         Understand sequential test pattern generation.
  • ·         Use various verification techniques.

Reference Books:

  • ·         Fault Tolerant and Fault Testable Hardware Design Parag K. Lala     BS Publication
  • ·         Principles of CMOS VLSI design N. Weste and K. Eshraghian Addison-Wesle

Book And Notes plz download the Book Link:- Parag K. Lala Book

Comments

Post a Comment

Popular posts from this blog

VLSI Lab Manual

Image
  VLSI Lab Manual VLSI Lab Manual List of Experiment 1.  Design of basic Gates: AND, OR, NOT using VHDL 2.  Design of basic Gates: AND, OR, NOT using VERILOG 3.  Design of 2:1 Mux using VHDL 4.  Design of 2:1 Mux using VERILOG 5.  Design of 2 to 4 Decoder using VHDL & VERILOG 6.  Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VHDL  7.  Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VERILOG  8.  Design of all type of Flip-Flops using VHDL (if-then-else)  9.  Design of all type of Flip-Flops using VERILOG 10. Design of 8-bit shift register using VHDL code 11. Design of 8-bit shift register using VERILOG 12. Design of Counters (MOD 3, MOD 5 etc.) using VHDL code 13. Design of counter using VERILOG code Experiment No.-1 Aim: Write VHDL code for basic gates: AND, OR, NOT. Apparatus: Xilinx ISE 14.1 software Theory: (1). AND Gate The AND gate is a basic digital logic...
Read more

M. Tech VLSI 3rd Semester Syllabus

Image
SEMESTER- 3 rd Course: M. Tech VLSI SUBJECT: System on Chip (SOC) Design Syllabus: Unit – I Recent advances in semiconductor technology, Programmable logic devices, such as field programmable gate arrays (FPGAs), Programmable chip architectures, logic synthesis, SoC concepts, and the Verilog synthesizable subset, Implementation of a complex system on a single programmable chip. Unit – II Tools and techniques for designing, verifying and implementing System-on-Chip (SoC) designs using programmable logic. Embedded system applications and their system-level hardware-software co-design. Unit – III Implementation Aspects: Adders, ALUs, Multipliers, Dividers, Register Files, Buses, CISC/RISC, Memory hierarchy (caches, MMU, main memory) Unit – IV ARM System-on-chip architecture. Unit - V Project Orientation: Concept to Verilog hardware description language (HDL),  verification using simulation, synthesis and programmable device implementation on an FPGA developme...
Read more

M. Tech. VLSI Reference Books

Image
  M. Tech. VLSI Reference Books Subject: Ad Mathematics Higher Engineering Mathematics B.V. Ramana Tata Mc Hill Advanced Engineering Mathematics Ervin Kreszig Wiley Easten Edd Applied Numerical Methods with MATLAB Steven C Chapra TMH George J. Klir and Yuan, B., Fuzzy sets and fuzzy logic, Theory and applications,   Prentice Hall of India Pvt. Ltd., 1997. Moon, T.K., Sterling, W.C., Mathematical methods and algorithms for signal processing,   Pearson Education, 2000. Richard Johnson, Miller & Freund’s Probability and Statistics for Engineers,   7 th   Edition, Prentice – Hall of India, Private Ltd., New Delhi (2007). Fuzzy Logics Book - Kwang H Lee  Question Bank for  Applied Mathematics for Electronics Engineers Subject: CMOS VLSI Design Basic VLSI Design D.A. Pucknell, K. EshraghianPHI, 3rd Ed Introduction to VLSI Circuits and Systems John P. Uyemura John Wiley & Sons Principles of CMOS VLSI Design Niel H.E. Weste, K.EshraghianPerson, 2nd Ed ...
Read more