VLSI Lab Manual
VLSI Lab Manual
List of Experiment
1. Design of basic Gates: AND, OR, NOT using VHDL
2. Design of basic Gates: AND, OR, NOT using VERILOG
3. Design of 2:1 Mux using VHDL
4. Design of 2:1 Mux using VERILOG
5. Design of 2 to 4 Decoder using VHDL & VERILOG
6. Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VHDL
7. Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VERILOG
8. Design of all type of Flip-Flops using VHDL (if-then-else)
9. Design of all type of Flip-Flops using VERILOG
10. Design of 8-bit shift register using VHDL code
11. Design of 8-bit shift register using VERILOG
12. Design of Counters (MOD 3, MOD 5 etc.) using VHDL code
13. Design of counter using VERILOG code
Experiment No.-1
Aim: Write VHDL code for basic gates: AND, OR, NOT.
Apparatus: Xilinx ISE 14.1 software
Theory:
(1). AND Gate The AND gate is a basic digital logic gate that implements logical conjuction – it behaves according to the truth table. A HIGH output (1) results only if both the inputs to the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results .
Fig 1. Logic diagram of AND gate
TRUTH TABLE
VHDL Code
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND1 is
Port (a : in STD_LOGIC; b : in STD_LOGIC;
c : out STD_LOGIC) ;
end AND1;
architecture behavioral of AND is begin
process (a,b) begin
if (a=‟1‟ and b=‟1‟) then
c<=‟1‟;
else
c<=‟0‟;
end if;
end process;
end behavioral;
(2).OR Gate - The OR gate is a digital logic gate that implements logical disjunction – it behaves according to the truth-table . A HIGH output (1) results if one
Fig 2. Logic diagram of OR gate
TRUTH TABLE
VHDL Code-
library IEEE;use
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity OR1 is
port (a,b : in STD_LOGIC;
c : out STD_LOGIC) ;
end OR1;
architecture behavioral of OR1 is
begin
process (a, b)
begin
if (a=‟0‟ and b=‟0‟)
then
c<=‟0‟;
else
c<=‟1‟;
end if;
end process;
end behavioral;
(3).NOT Gate - In digital logic , an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown below.
Fig 3. Logic diagram of NOT gate
TRUTH TABLE
VHDL Code-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NOT1 is
port (a : in STD_LOGIC;
c : out STD_LOGIC) ;
end NOT1;
architecture behavioral of NOT1 is
begin
process (a)
begin
if (a=‟0”) then
c<=‟1‟;
else
c<=‟0‟;
end if;
end process;
end behavioural;
Experiment No.-2
AIM: Write verilog code for two input logic gate
Apparatus: Xilinx ISE 14.1 software
Verilog code –
module gate2(a,b,x);
input a,b;
output x;
1. and(x,a,b); // 2- input Logic gates
2. or(x,a,b);
3. not(x,a); // only one input for NOT
endmodule
Experiment No.-3
Aim: Write VHDL code for 2:1 MUX
Apparatus: Xilinx ISE 14.1 software
Theory :
2:1 mux
A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line.
TRUTH TABLE
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_2 to 1 is
port (a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC z : out STD_LOGIC) ; end mux_2 to 1 is;
architecture behavioral of mux_2 to 1 is begin
process (a, b, s) begin
if (s=‟0‟)then
z<=a;
else
z<=b;
end if;
end process;
end behavioral;
Experiment No.-4
Aim: Write Verilog code for 2:1 MUX
Apparatus: Xilinx ISE 14.1 software
Verilog code -
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
reg f;
assign f = s ? w1 : w0;
always @(w0 or w1 or s)
f = s ? w1 : w0;
always @(w0 or w1 or s)
if (s==0)
f = w0;
else
f = w1;
endmodule
Experiment No.-5
Aim : (i) Write VHDL code for 2 to 4 Decoder.
(ii) Write a Verilog code for 2 to 4 Decoder.
Apparatus : Xilinx ISE 14.1 software
Theory :
Decoder A decoder is a combinational circuit that converts binary information from n inputs line to a maximum of 2^n unique output lines.
TRUTH TABLE
(I) VHDL CODE :
library IEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_2_to_4 is
port (a : in STD_LOGIC_VECTOR; E : in STD_LOGIC; d : out STD_LOGIC_VECTOR (3 downto 0) ;
end decoder_2_to_4 ;
architecture behavioral of decoder_2_to_4 is begin
process (a)
begin case a is
when “00”=> d<=“0001”;
when “01”=> d<=“0010”;
when “10”=> d<=“0100”;
when others=> d<=“1000”;
end case;
end process;
end behavioral;
(II) VERILOG CODE :
module dec2to4 (W, Y, En);
input [1:0]W; // Address lines
input En; // Enable
output [0:3]Y;
reg [0:3]Y;
always @(W or En)
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
if (En == 0)
Y = 4'b0000;
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
always @(W or En)
for (k = 0; k <= 3; k = k+1)
if ((W == k) && (En == 1))
Y[k] = 1;
else
Y[k] = 0;
not n1(r1,W[1]);
not n2(r2,W[0]);
and a1(Y[1],r1,r2);
and a2(Y[2],r1,W[0]);
and a3(Y[3],r2,W[1]);
and a4(Y[4],W[1],W[0]);
endmodule
Experiment No.-6
Aim: Write VHDL code for Half-Adder, Full-Adder, Half Substractor , Full Substractor
Apparatus: Xilinx ISE 14.1 software
(I)Half-adder : The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.
Fig 10. Logic Daigram of Half -Adder
Truth Table
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity half_adder is
port (a : in STD_LOGIC; b : in STD_LOGIC;
s,c : out STD_LOGIC);
endhalf_adder;
architecture behavioral of half_adder is
begin
if (a=‟0‟ and b=‟0‟)
then
s<=‟0‟;
c<=‟0‟;
elsif (a=‟1‟ and b=‟1‟)
s<=‟0‟;
c<=‟1‟;
else
s<=‟1‟;
c<=‟0‟;
end if;
end process;
end behavioral;
Full-Adder: A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less-significant stage
Fig 11. Logic Daigram Of Full-Adder
Truth Table of Full-Adder
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity full_adder is
port (a : in STD_LOGIC_VECTOR (0 to 2);
s : out STD_LOGIC_VECTOR (0 to 1));
end full_adder;
architecture behavioral of full_adder is
begin Truth table for full-adder process (a)
begin case a is
when “000”=> s<=“00”;
when “001”=> s<=“10”;
when “010”=> s<=“10”;
when“011”=> s<=“01”;
when “100”=> s<=“10”;
when “101”=> s<=“01”;
when “110”=> s<=“01”;
whenothers =>s<=“11”;
end case;
end process;
end behavioral;
Half-substractor:
Fig . Half Substractor
Truth table:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; useIEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_subs is
port (a,b : in STD_LOGIC;
d, b1: out STD_LOGIC);
end half_subs
architecture behavioral of half_subs is
begin
process (a,b)
begin
if (a=b)
then
d<=‟0‟;
end if;
if (a=‟0‟ and b=‟1‟)
then
b1<=‟1‟;
else
b1<=‟0‟;
end if;
end process;
end behavioral;
Full-Substractor:
Truth Table
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full_subs is
port (a : in STD_LOGIC_VECTOR (0 to 2);
s : out STD_LOGIC_VECTOR (0 to 1));
end full_subs;
Truth-table for full-substractor: architecture behavioral of
full_subs is begin
process (a)
begin
case a is
when “000”=> s<=“00”;
when “001”=> s<=“11”;
when “010”=> s<=“11”;
when “011”=> s<=“01”;
when “100”=> s<=“10”;
when “101”=> s<=“00”;
when “110”=> s<=“00”;
when others =>s<=“11”;
end case;
end process;
end behavioral;
Experiment No.-7
Aim: Write Verilog code for Half-Adder, Full-Adder, Half Substractor , Full Substractor
Apparatus: Xilinx ISE 14.1 software
Theory:
(I)Half-adder : The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.
Fig 10. Logic Daigram of Half -Adder
Truth Table
Verilog Code
module halfadder(sum,carryout,in0,in1);
input ino,in1;
output sum,carryout;
xor x1(s,a,b);
and a1(c,a,b);
assign sum = a ^ b;
assign carryout = (a & b);
endmodule
Full-Adder: A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less-significant stage
Fig 11. Logic Daigram Of Full-Adder
Truth Table of Full-Adder
Verilog Code :
module fulladder (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
reg s, Cout;
assign s = x ^ y ^ Cin; //concurrent dataflow
assign Cout = (x & y) | (x & Cin) | (y & Cin);
always @(x or y or Cin) // Sequential
{Cout, s} = x + y + Cin;
xor (z4, x, y); // Using Primitives
xor (s, z4, Cin); // wire z1,z2,z3,z4 ; connecting wires
and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);
xor (s, x, y, Cin); //3-input xor
and (z1, x, y), (z2, x, Cin),(z3, y, Cin); //multiple instantiations
or (Cout, z1, z2, z3);
endmodule
Half-substractor: The Half Substractor is a combinational circuit which is used to perform substraction of two bits. It has two inputs , the minued and subtrahend and two outputs the difference and borrow out.
Fig . Half Substractor
Truth table:
Verilog Code:
module halfsubs(diff,borrow,in0,in1);
input ino,in1;
output diff,borrow;
xor x1(d,x,y);
and a1(b,x,y);
assign diff = x ^ y;
assign borrow = ((~x)&y);
endmodule
Full-Substractor: The Full Substractor is a combinational circuit which is usedto perform substraction of three input bits : the minuend , subtrahend and borrow in. The full substractor generates two output bits : the difference and borrow out(is set when the previous digit borrowed from)
Truth Table
Verilog Code
module fullsub(x1,x2,x3,d,b);
input x1,x2,x3;
output d,b;
assign d= x1^x2^x3;
assign b=(~x1)&((x1^x3)|(x2&x3));
endmodule
Experiment No.-8
Aim: Write VHDL code for S-R Flip-Flops
Apparatus: Xilinx ISE 14.1 software
S-R flip-flop:
TRUTH TABLE
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity flipflop_SR is
port (s, r, clk, rst : in std_logic;
q : out std_logic);
end flipflop_SR;
architecture behavioral of flipflop_SR is begin
process (s, r, clk, rst) begin
if (clk= „1‟ and clk‟event)
then if (rst= „1‟)
then
q<= „0‟;
elsif (rst= „0‟)
then
q<= „1‟;
elsif (s= „0‟ and r= „0‟ and rst= „0‟)
then
q<=q;
elsif (s= „0‟ and r= „1‟ and rst= „0‟)
then
q<= „0‟;
elsif (s= „1‟ and r= „0‟ and rst= „0‟)
then
q<= „1‟;
elsif (s= „1‟ and r= „1‟ and rst= „0‟)
then
q<= „U‟;
end if;
end if;
end process;
end behavioral;
Experiment No.-9
Aim: Write a Verilog code for S-R Flip-Flops
Apparatus: Xilinx ISE 14.1 software
S-R flip-flop:
TRUTH TABLE
Verilog Code
module rsff(q,s,r,clr,clk);
input s,r,clk,clr;
output q;
reg q;
initial q=1'b 0;
always@(r or s or clk or clr)
begin
if(clk==1 && clr==0)
begin
if(s==0 && r==0)
q=q;
else
if((s==0 && r==1) || (s==1 && r==0))
q=s;
else
if(s==1 && r==1)
$display("Undefined operation performed");
else
q=q;
end
end
endmodule
Experiment No.-10
Aim: Write a VHDL code for 8-bit shift register
Apparatus: Xilinx ISE 14.1 software
Theory: The term register can be used in variety of specific applications, but in all cases it refers to a group of flip-flops operating as a coherent unit to hold data. This is different from counter, which is a group of flip-flops operating to generate new data by tabulating it.
The demonstration circuit below is known as shift register because data is shifted through it, from flip-flop to flip-flop. If we apply 8-bits of data to the initial data input and apply one clock pulse to the circuit after setting each bit of data, we will find the entire byte present at the flip-flop outputs in parallel format. Therefore, this circuit is known as a serial-in, parallel-out shift register.
Fig. Logic diagram of 8-bit shift register
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity eftshift is
port (a : inoutbit_vector (0 to 7);
r, l, rst, load, clk : in bit;
q : out bit_vector (0 to 7));
end leftshift;
architecture behavioral of leftshift is begin
process (load, rst, a, clk) begin
if (clk= „1‟ and clk‟event) then
if (load= „1‟)
then
q<=a;
elsif(load= „0‟)
then
if (rst= „1‟)
then q<= “00000000”;
elseif (l= „1‟) then
q<=a slll;
end if;
if (r= „1‟) then
q<= a srll;
end if;
end if;
end if;
end if;
end process;
end behavioural;
Experiment No.-11
Aim : Write a Verilog code for 8-bit shift register.
Apparatus : Xilinx ISE 14.1 software
Theory : The term register can be used in variety of specific applications, but in all cases it refers to a group of flip-flops operating as a coherent unit to hold data. This is different from counter, which is a group of flip-flops operating to generate new data by tabulating it.
The demonstration circuit below is known as shift register because data is shifted through it, from flip-flop to flip-flop. If we apply 8-bits of data to the initial data input and apply one clock pulse to the circuit after setting each bit of data, we will find the entire byte present at the flip-flop outputs in parallel format. Therefore, this circuit is known as a serial-in, parallel-out shift register
Fig . Logic diagram of 8-bit shift register
Verilog Code
module shift_reg(out,in,load,clk);
output [7:0]out;
input [7:0]in;
input clk;
input load;
reg [7:0]out;
wire [7:0]in;
always@(posedge clk)
begin
if(load)
begin
out<=in;
end
else
begin
out[0]<=out[7];
out[1]<=out[0];
out[2]<=out[1];
out[3]<=out[2];
out[4]<=out[3];
out[5]<=out[4];
out[6]<=out[5];
out[7]<=out[6];
end
end
endmodule
Experiment No.-12
Aim: Write a VHDL code for Counters (MOD 3, MOD 5 ,MOD 7)
Apparatus: Xilinx ISE 14.1 software
Theory : A sequential circuit that goes through a prescribed sequence of states upon application of input pulse is called a counter. A counter that follows binary sequence is called binary counter.
Synchronous counter: In synchronous counters all flip-flops are given common clock pulse.
Asynchronous counter: In this type of counter the output of one flip-flop acts as a clock for
next flip-flop.
MOD 3 Counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod3 is
port (clk, rst : in std_logic;
c : out std_logic_vector (0 to 1));
end mod3;
architecture behavioral of mod3 is signal a : std_logic_vector (0 to 1):= “00”; signal clock : std_logic:= „0‟;
begin
process (clk, rst) variable d : integer:= 0;
--variable clock : std_logic; begin
if (clk= „1‟ and clk‟event)
then
d := d+1;
if (d=10000000) then
clock<= not clock;
d := 0;
end if;
end if;
end process;
process (clock, rst)
variable a : std_logic_vector (0 to 1) := “00”;
begin
if (rst = „1‟) then a := “00”;
end if;
a := a+ “01”;
if (a = “11”) then
a := “00”;
end if;
end if;
c <= a;
end process;
end behavioral;
MOD 5 Counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod5is
port (clk, rst : in std_logic;
c : out std_logic_vector (0 to 2));
end mod5;
architecture behavioral ofmod5is signal clock : std_logic:= „0‟; begin
process (clk, rst) variable d : integer:= 0;
--variable clock : std_logic; begin
if (clk= „1‟ and clk‟event) then
d := d+1;
if (d=10000000) then
clock<= not clock;
d := 0;
end if;
end if;
end process;
process (clock, rst)
variable a : std_logic_vector (0 to 2) := “000”;
begin
if (rst = „1‟) then a := “000”;
elsif(rising_edge (clock))
then
a := a+ “001”;
if (a = “100”) then a := “000”;
end if;
end if;
c <= a;
end process;
end behavioral;
MOD 7 Counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod7 is
port (clk, rst : in std_logic;
c : out std_logic_vector (0 to 2));
end mod7;
architecture behavioral of mod7 is
signal a : std_logic_vector (0 to 2) := “000”; signal clock : std_logic:= „0‟;
begin
process (clk, rst)
variable d : integer:= 0;
--variable clock : std_logic;
Begin
if (clk= „1‟ and clk‟event) then
d := d+1;
if (d=10000000) then
clock<= not clock;
d := 0;
end if;
end if;
end process;
process (clock, rst)
variable a : std_logic_vector (0 to 2) := “000”;
begin
if (rst = „1‟) then a := “000”;
elsif(rising_edge (clock))
then
a := a+ “001”;
if (a = “111”) then a := “000”;
end if;
end if;
c <= a;
end process;
end behavioral;
Experiment No.-13
Aim : Write a Verilog code for Counters .
Apparatus : Xilinx ISE 14.1 software
Introduction : A sequential circuit that goes through a prescribed sequence of states upon application of input pulse is called a counter. A counter that follows binary sequence is called binary counter.
Up counter
module upcount(R, Resetn, Clock, E, L, Q);
input [3:0] R;
input Resetn, Clock, E, L;
output [3:0] Q;
reg [3:0] Q;
always @(negedge Resetn or posedge Clock)
if (!Resetn)
Q <= 0;
else if (L)
Q <= R;
else if (E)
Q <= Q + 1;
endmodule
Up-down counter
module updowncount(R, Clock, L, E, up_down, Q);
parameter n=8;
input [n-1:0] R;
input Clock, L, E, up_down;
output [n-1:0] Q;
reg [n-1:0] Q;
integer direction;
always @(posedge Clock)
begin
if (up_down)
direction = 1;
else
direction = -1;
if (L)
Q <= R;
else if (E)
Q <= Q + direction;
end
endmodule
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