VLSI

Very Long Instruction Word (VLIW) Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel. Or Very long instruction word (VLIW) is an instruction set architecture designed to take full advantage of instruction-level parallelism (ILP) for improved performance. Central processing units (CPU, processor) allow programs to specify instructions to execute in sequence only whereas a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs. VLIW is sometimes viewed as the next step beyond the reduced instruction set computing ( RISC ) architecture, which also works with a limited set of relatively basic instructions and can usually execute more than one instruction at a time. The main a...

  VLSI Lab Manual VLSI Lab Manual List of Experiment 1.  Design of basic Gates: AND, OR, NOT using VHDL 2.  Design of basic Gates: AND, OR, NOT using VERILOG 3.  Design of 2:1 Mux using VHDL 4.  Design of 2:1 Mux using VERILOG 5.  Design of 2 to 4 Decoder using VHDL & VERILOG 6.  Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VHDL  7.  Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VERILOG  8.  Design of all type of Flip-Flops using VHDL (if-then-else)  9.  Design of all type of Flip-Flops using VERILOG 10. Design of 8-bit shift register using VHDL code 11. Design of 8-bit shift register using VERILOG 12. Design of Counters (MOD 3, MOD 5 etc.) using VHDL code 13. Design of counter using VERILOG code Experiment No.-1 Aim: Write VHDL code for basic gates: AND, OR, NOT. Apparatus: Xilinx ISE 14.1 software Theory: (1). AND Gate The AND gate is a basic digital logic...