VLSI Lab Manual
VLSI Lab Manual VLSI Lab Manual List of Experiment 1. Design of basic Gates: AND, OR, NOT using VHDL 2. Design of basic Gates: AND, OR, NOT using VERILOG 3. Design of 2:1 Mux using VHDL 4. Design of 2:1 Mux using VERILOG 5. Design of 2 to 4 Decoder using VHDL & VERILOG 6. Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VHDL 7. Design of Half-Adder, Full Adder, Half Substractor, Full Substractor using VERILOG 8. Design of all type of Flip-Flops using VHDL (if-then-else) 9. Design of all type of Flip-Flops using VERILOG 10. Design of 8-bit shift register using VHDL code 11. Design of 8-bit shift register using VERILOG 12. Design of Counters (MOD 3, MOD 5 etc.) using VHDL code 13. Design of counter using VERILOG code Experiment No.-1 Aim: Write VHDL code for basic gates: AND, OR, NOT. Apparatus: Xilinx ISE 14.1 software Theory: (1). AND Gate The AND gate is a basic digital logic...

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