VLSI

Assignment–1 Q1. Explain the internal structure of CPLD. How the output is considered to be the registered output? Q2. What are the classical techniques for reducing the complexity of IC design? Explain each of them. Q3. Compare VLSI Design Style with FPGA and CPLD? Q4. Explain complete VLSI Design flow with all domains. Q5. Explain the FPGA. Q6. Explain the CPLD. Q7. Explain the design hierarchy concept of regularity, modularity and locality. Assignment-2 Q1. Draw the stick diagram of CMOS inverter. Q2. What are the reasons behind different design rules in layout. Q3. Draw the symbolic layout of a 2-input NOR gate. Q4. Explain basic steps for fabrication of CMOS Q5. Calculation of resistance and capacitance. Q6. Explain the Layout design rules. Q7. Explain fabrication process of PMOS & Bi-CMOS Assignment-3 Q1. Draw the three transistor dynamic RAM cell also. Draw the Stick diagram for the same using CMOS Technology. Q2. Explain the ROM Designing techniques with different symbolic ...

 

Analog VLSI Design REFERENCES: 1. Mohammed Ismail, Terri Fief, “Analog VLSI Signal and Information Processing ", McGraw- Hill International Editons, 1994. 2. Malcom R.Haskard, Lan C. May, “Analog VLSI Design - NMOS and CMOS ", Prentice-Hall, 1998. 3. Randall L Geiger, Phillip E. Allen, Noel K. Strader, “ VLSI Design Techniques for Analog and Digital Circuits ", Mc Graw Hill International Company, 1990.  Download link –   Download   4. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI Circuits for Telecommunication and Signal Processing ", Prentice-Hall, 1994 Extra Materials: 1. Mixed Analog-Digital VLSI Devices and Technology by Yannis Tsividis.  Download Link -  Download IP-Based VLSI Design REFERENCES: 1. Wayne wolf, “Modern VLSI Design: IP-based Design”, Pearson Education,2009.  Download link -  Download 2. Qu gang, Miodrag potkonjak, “Intellectual Property Protection in VLSI Designs:...

  The difference between the two Logic Styles are: TTL  circuits utilize  BJTs  while  CMOS  circuits utilize  FETs . CMOS  allows a much higher density of logic functions in a single chip compared to  TTL . TTL  circuits consumes more power compared to  CMOS  circuits at rest.   CMOS  chips are a lot more susceptible to static discharge compared to  TTL  chips Propagation delay is more in  CMOS  compared to  TTL Switching Speed is More for  TTL  compared to  CMOS . CMOS  devices are cheaper than  TTL  Devices.  The Power Supply requirement for  TTL  is  3 to 15V, small fluctuations are tolerated. The Power Supply requirement for  CMOS  is   5V ±0.25V, it must be very smooth, a regulated supply. TTL  Can handle only less frequency compared to  CMOS . Why CMOS is Slower compared to TTL? Since TTL has very little parasiti...